ARM CPU Hardening Lead

Category: Semiconductor
Job ID: P-108689
widget: Full-Time

Description

Job Requirements

1. Lead – High Performance ARM Core Hardening

 

Job Title: Lead Engineer – ARM Core Hardening

Location: BLR/Hyd

Experience: 8–12 years

Technology Node: 5nm/3nm/2nm FinFET/GAA

Reports To: Director/Technical Manager – SoC Implementation

 

Key Responsibilities:

Lead end-to-end RTL-to-GDSII hardening of ARM Cortex-A/X/Neoverse cores (single and multi-cluster).

Collaborate with RTL, CAD, DFT, low power, and architecture teams to define floorplan and implementation strategy.

Own full flow: floorplanning, power planning (UPF-based), placement, CTS, routing, ECO, timing closure, physical verification, and signoff.

 

Drive design quality metrics: PPA (Performance, Power, Area), DRC/LVS clean, IR drop, EM, and thermal-aware optimization.

Architect physical implementation methodology tailored to ARM hardening: hierarchical flow, black-boxing strategy, physical partitioning, clocking architecture.

Interface with foundry and EDA vendors for process tech enablement and tool issues.

Technical Skills:

Deep understanding of ARM core microarchitecture (pipeline, fetch/decode, FPU/NEON, L1/L2 cache).

Expert in Synopsys/Cadence tools: ICC2/Fusion Compiler, Tempus/Innovus, Primetime, StarRC, RedHawk/Totem.

Advanced clock tree design: CCOpt, custom H-trees, mesh, and multi-source CTS.

Experience with UPF-based low power flows and Conformal Low Power (CLP) verification.

Familiarity with physical-aware DFT and scan compression (test-mode aware synthesis/placement).

Familiar with physical architecture trade-offs (voltage islands, power domains, channel management).

Knowledge of EMIR, thermal, aging-aware closure in HPC-class cores.

Experience taping out at 5nm or lower is mandatory.

 

---

2. Engineer – ARM Core Hardening

Job Title: Physical Design Engineer – ARM Core Hardening

Location: BLR/Hyd

Experience: 3–8 years

Technology Node: 5nm/3nm/2nm FinFET/GAA

Key Responsibilities:

Implement physical design of ARM core and subsystems from RTL to GDSII.

Responsible for floorplanning, placement, CTS, routing, timing and physical closure of core logic.

Perform static timing analysis, IR/EM validation, and physical verification.

Optimize for frequency, leakage, and area within power and thermal budgets.

Support integration of hardened cores into SoC top-level environment.

Technical Skills:

Good understanding of ARM core architecture and pipeline structure.

Experience in Synopsys or Cadence PnR and signoff tools (ICC2, Fusion Compiler, Innovus, PT, RedHawk).

Experience in UPF flows, CPF/UPF constraints, and low-power verification tools.

Good in timing ECOs, DFT integration, scan reordering and hold fixing in low power designs.

Strong debugging skills: congestion, IR drop, setup/hold, crosstalk, antenna, and DRC.

Familiar with scripting (TCL, Python, Perl) to automate flows and reports.

 



Work Experience

 

 Lead – High Performance ARM Core Hardening

Experience working with ARM POP (Processor Optimization Pack) or ARM Artisan Physical IP.

Worked with multi-core cluster hardening and coherent interconnects (e.g., CMN-600).

Experience with RTL-based performance modeling and correlation with implementation

 

ARM Core Engineer:

ARM POP usage experience.

Previous tapeout at ≤7nm.

Exposure to hierarchical and multi-voltage designs.

Familiarity with advanced floorplanning constraints for multi-core clusters.



Get notified for similar jobs

Sign up to receive job alerts
Get tailored job recommendations based on your interests.

Currently we dont have enough information to provide personalized job recommendations.

Life at Quest Global

We’re working together to build strong communities inside and outside.
Culture
We’re working together to build strong communities inside and outside.
Benefits
Company sees the whole person and looks to support your well-being.
Diversity and Inclusion
We value individuality. experiences that have shaped your world.