Senior Engineer - Analog Design

Location: Bengaluru, Karnataka, India
Category: Semiconductor
Job ID: P-108921
widget: Full-Time

Description

Job Requirements

Role:

Design, simulate, and verify transistor-level analog circuits for Phase-Locked Loops (PLLs), including key blocks such as VCOs, charge pumps, loop filters, and phase/frequency detectors. Collaborate with cross-functional teams to integrate PLLs into advanced semiconductor products and ensure high performance and reliability.

Key Responsibilities:

- Design and develop analog PLL circuits at the transistor level, focusing on VCOs, charge pumps, loop filters, and phase/frequency detectors.

- Use CADENCE simulation tools, MATLAB for circuit design, modeling, and verification.

- Perform circuit simulations to validate functionality, performance, and reliability; optimize designs based on simulation and test results.

- Collaborate with layout engineers to ensure robust physical design, addressing parasitics, noise, and signal integrity.

- Develop and execute test plans for prototype validation; analyze test data and iterate on designs as needed.

- Document design specifications, schematics, simulation results, and test reports; participate in design reviews.

Qualifications:

- Bachelor’s or Master’s degree in Electrical Engineering or related field.

- Strong understanding of analog and mixed-signal circuit design, with direct experience in PLL architectures and transistor-level design.

- Excellent problem-solving, documentation, and communication skills.

- 3+ years of relevant experience preferred; advanced degrees or additional experience are advantageous.

 

**Preferred Skills:**

- Experience with high-frequency PLLs (e.g., >10GHz), spread-spectrum clocks, or advanced CMOS/FinFET processes[2][3].

- Familiarity with digital design tools (e.g., Verilog) and mixed-signal integration[2][3].

- Project management and mentoring abilities are a plus[3].



Work Experience

Role:

Design, simulate, and verify transistor-level analog circuits for Phase-Locked Loops (PLLs), including key blocks such as VCOs, charge pumps, loop filters, and phase/frequency detectors. Collaborate with cross-functional teams to integrate PLLs into advanced semiconductor products and ensure high performance and reliability.

Key Responsibilities:

- Design and develop analog PLL circuits at the transistor level, focusing on VCOs, charge pumps, loop filters, and phase/frequency detectors.

- Use CADENCE simulation tools, MATLAB for circuit design, modeling, and verification.

- Perform circuit simulations to validate functionality, performance, and reliability; optimize designs based on simulation and test results.

- Collaborate with layout engineers to ensure robust physical design, addressing parasitics, noise, and signal integrity.

- Develop and execute test plans for prototype validation; analyze test data and iterate on designs as needed.

- Document design specifications, schematics, simulation results, and test reports; participate in design reviews.

Qualifications:

- Bachelor’s or Master’s degree in Electrical Engineering or related field.

- Strong understanding of analog and mixed-signal circuit design, with direct experience in PLL architectures and transistor-level design.

- Excellent problem-solving, documentation, and communication skills.

- 3+ years of relevant experience preferred; advanced degrees or additional experience are advantageous.

 

**Preferred Skills:**

- Experience with high-frequency PLLs (e.g., >10GHz), spread-spectrum clocks, or advanced CMOS/FinFET processes[2][3].

- Familiarity with digital design tools (e.g., Verilog) and mixed-signal integration[2][3].

- Project management and mentoring abilities are a plus[3].





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